CS4954-CQ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS4954-CQ

NTSC/PAL Digital Video Encoder

Cirrus Logic 

CS4954 CS4955

9. BOARD DESIGN AND LAYOUT

CONSIDERATIONS

The printed circuit layout should be optimized for

lowest noise on the CS4954/5 placed as close to the

output connectors as possible. All analog supply

traces should be as short as possible to minimize in-

ductive ringing.

A well designed power distribution network is es-

sential in eliminating digital switching noise. The

ground planes must provide a low-impedance re-

turn path for the digital circuits. A PC board with a

minimun of four layers is recommended. The

ground layer should be used as a shield to isolate

noise from the analog traces. The top layer (1)

should be reserved for analog traces but digital

traces can share this layer if the digital signals have

low edge rates and switch little current or if they are

separated from the analog traces by a signigicant

distance (dependent on their frequency content and

current). The second layer should then be the

ground plane followed by the analog power plane

on layer three and the digital signal layer on layer

four.

9.1. Power and Ground Planes

The power and ground planes need isolation gaps

of at least 0.05" to minimize digital switching noise

effects on the analog signals and components. A

split analog/digital ground plane should be con-

nected at one point as close as possible to the

CS4954/5.

9.2. Power Supply Decoupling

Start by reducing power supply ripple and wiring

harness inductance by placing a large (33-100 uF)

capacitor as close to the power entry point as pos-

sible. Use separate power planes or traces for the

digital and analog sections even if they use the

same supply. If necessary, further isolate the digital

and analog power supplies by using ferrite beads on

each supply branch followed by a low ESR capac-

itor.

Place all decoupling caps as close as possible the

the device as possible. Surface mount capacitors

generally have lower inductance than radial lead or

axial lead components. Surface mount caps should

be place on the component side of the PCB to min-

imize inductance caused by board vias. Any vias,

especially to ground, should be as large as possible

to reduce their inductive effects.

9.3. Digital Interconnect

The digital inputs and outputs of the CS4954/5

should be isolated from the analog outputs as much

as possible. Use separate signal layers whenever

possible and do not route digital signals over the

analog power and ground planes.

Noise from the digital section is related to the digi-

tal edge rates used. Ringing, overshoot, under-

shoot, and ground bounce are all related to edge

rate. Use lower speed logic such as HCMOS for the

host port interface to reduce switching noise. For

the video input ports, higher speed logic is re-

quired, but use the slowest practical edge rate to re-

duce noise. To reduce noise, it is important to

match the source impedance, line impedance, and

load impedance as much as possible. Generally, if

the line length is greater than one fourth the signal

edge rate, line termination is necessary. Ringing

can also be reduced by damping the line with a se-

ries resistor (22-150 Ω). Under extreme cases, it

may be advisable to use microstrip techniques to

further reduce radiated switching noise if very fast

edge rates (<2ns) are used. If microstrip techniques

are used, split the analog and digital ground planes

and use proper RF decoupling techniques.

9.4. Analog Interconnect

The CS4954/5 should be located as close as possi-

ble the output connectors to minimize noise pickup

and reflections due to impedance mismatch. All un-

used analog outputs should be placed in shutdown.

This reduces the total power that the CS4954/5 re-

quires, and eliminates the impedance mismatch

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DS278PP4

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