ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADV7194KST
(Rev.:Rev0)

Professional Extended-10 Video Encoder with 54 MHz Oversampling

Analog Devices 

ADV7194

TR17

TR16

TR15

TR14

TR13

TR12

TR11

TR10

HSYNC TO PIXEL

DATA ADJUST

TR17 TR16

0 0 0 ؋ TPCLK

0 1 1 ؋ TPCLK

1 0 2 ؋ TPCLK

1 1 3 ؋ TPCLK

HSYNC TO VSYNC

RISING EDGE DELAY

(MODE 1 ONLY)

TR15 TR14

؋0

؋1

TC

TB

TB + 32␮s

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0 0 1 ؋ TPCLK

0 1 4 ؋ TPCLK

1 0 16 ؋ TPCLK

1 1 128 ؋ TPCLK

TIMING MODE 1 (MASTER/PAL)

LINE 1

HSYNC

TA

TB

VSYNC

HSYNC TO

VSYNC DELAY

TR13 TR12

TB

0 0 0 ؋ TPCLK

0 1 4 ؋ TPCLK

1 0 8 ؋ TPCLK

1 1 18 ؋ TPCLK

HSYNC WIDTH

TR11 TR10

TA

0

0 1 ؋ TPCLK

0 1 4 ؋ TPCLK

1 0 16 ؋ TPCLK

1 1 128 ؋ TPCLK

LINE 313

TC

LINE 314

Figure 67. Timing Register 1

SUBCARRIER FREQUENCY REGISTERS 3–0

(FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH)

These 8-bit-wide registers are used to set up the Subcarrier Fre-

quency. The value of these registers are calculated by using the

following equation:

( ) Subcarrier Frequency Register = 232 – 1 × fSCF

fCLK

Example: NTSC Mode, fCLK = 27 MHz, fSCF = 3.5795454 MHz

( ) 232 – 1 × 3.5795454 × 106

Subcarrier Frequency Value =

27 × 106

Subcarrier Register Value = 21F07C16 Hex

Figure 68 shows how the frequency is set up by the four registers.

SUBCARRIER

FREQUENCY

REG 3

SUBCARRIER

FREQUENCY

REG 2

SUBCARRIER

FREQUENCY

REG 1

SUBCARRIER

FREQUENCY

REG 0

FSC31

FSC23

FSC15

FSC7

FSC30

FSC22

FSC14

FSC6

FSC29

FSC21

FSC13

FSC5

FSC28

FSC20

FSC12

FSC4

FSC27

FSC19

FSC11

FSC3

FSC26

FSC18

FSC10

FSC2

FSC25

FSC17

FSC9

FSC1

FSC24

FSC16

FSC8

FSC0

Figure 68. Subcarrier Frequency Registers

SUBCARRIER PHASE REGISTER (FPH7–FPH0)

(Address (SR4–SR0) = 10H)

This 8-bit-wide register is used to set up the Subcarrier Phase.

Each bit represents 1.41°. For normal operation this register is

set to 00Hex.

SUBCARRIER

PHASE FPH7

REGISTER

FPH6

FPH5

FPH4

FPH3

FPH2

FPH1

FPH0

Figure 69. Subcarrier Phase Register

CLOSED CAPTIONING EVEN FIELD

DATA REGISTER 1–0 (CCD15–CCD00)

(Address (SR4–SR0) = 11–12H)

These 8-bit-wide registers are used to set up the closed captioning

extended data bytes on Even Fields. Figure 70 shows how the

high and low bytes are set up in the registers.

BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

Figure 70. Closed Captioning Extended Data Register

CLOSED CAPTIONING ODD FIELD

DATA REGISTER 1–0 (CCD15–CCD0)

(Subaddress (SR4–SR0) = 13–14H)

These 8-bit-wide registers are used to set up the closed captioning

data bytes on Odd Fields. Figure 71 shows how the high and low

bytes are set up in the registers.

BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

BYTE 0 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

Figure 71. Closed Captioning Data Register

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS 3–0

(PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)

(Subaddress (SR4–SR0) = 15–18H)

These 8-bit-wide registers are used to enable the NTSC pedes-

tal/PAL Teletext on a line by line basis in the vertical blanking

interval for both odd and even fields. Figures 68 and 69 show

the four control registers. A Logic 1 in any of the bits of these

registers has the effect of turning the Pedestal OFF on the

equivalent line when used in NTSC. A Logic 1 in any of the

bits of these registers has the effect of turning Teletext ON on

the equivalent line when used in PAL.

REV. 0

–37–

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