ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7194KST Datasheet PDF : 69 Pages
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RESET
DAC D,
DAC E
XXXXXXX
DAC F XXXXXXX
DAC A,
DAC B,
DAC C
XXXXXXX
MR26
PIXEL_DATA_VALID
XXXXXXX
XXXXXXX
XXXXXXX
OFF
0
BLACK VALUE WITH SYNC
BLACK VALUE
DIGITAL TIMING
XXXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
Figure 36. RESET Sequence Timing Diagram
ADV7194
VALID VIDEO
VALID VIDEO
VALID VIDEO
1
TIMING ACTIVE
RTC
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
VIDEO LCC1 GLL
DECODER
ADV7185
P19–P12
M
U
X
MPEG
DECODER
H/L TRANSITION
COUNT START
LOW
128
13
14 BITS
RESERVED
4 BITS
RESERVED
0
21
CLOCK
ADV7194
SCRESET/RTC/TR
P9–P0
HSYNC
FIELD/ VSYNC
GREEN / COMPOSITE / Y
BLUE / LUMA / U
RED / CHROMA / V
GREEN / COMPOSITE / Y
BLUE / LUMA / U
RED / CHROMA / V
FSCPLL INCREMENT1
SEQUENCE
BIT2
5 BITS
RESERVED
RESET
BIT3
RESERVED
0
TIME SLOT: 01
14
19
NOT USED IN
ADV7194
VALID INVALID
SAMPLE SAMPLE
8 / LINE
LOCKED CLOCK
67 68
NOTES:
1FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7194 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY
REGISTERS OF THE ADV7194.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7194’s DDS
Figure 37. RTC Timing and Connections
REV. 0
–21–
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