ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADV7194KST Datasheet PDF : 69 Pages
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ADV7194
MPU PORT DESCRIPTION
The ADV7194 supports a 2-wire serial (I2C-compatible) micro-
processor bus driving multiple peripherals. Two inputs Serial
Data (SDA) and Serial Clock (SCL) carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7194 has four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 51 and
Figure 53. The LSB sets either a read or write operation. Logic
Level 1 corresponds to a read operation while Logic Level 0
corresponds to a write operation. A1 is set by setting the ALSB
pin of the ADV7194 to Logic Level 0 or Logic Level 1. When
ALSB is set to 0, there is greater input bandwidth on the I2C
lines, which allows high speed data transfers on this bus. When
ALSB is set to 1, there is reduced input bandwidth on the I2C
lines, which means that pulses of less than 50 ns will not pass
into the I2C internal controller. This mode is recommended for
noisy systems.
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SETUP BY
ALSB
READ / W RITE
CONTROL
0
WRITE
1
READ
Figure 51. Slave Address
To control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high to low transition on
SDA while SCL remains high. This indicates that an address/data
stream will follow. All peripherals respond to the start condition
and shift the next eight bits (7-bit address + R/W bit). The bits are
transferred from MSB down to LSB. The peripheral that recog-
nizes the transmitted address responds by pulling the data line
low during the ninth clock pulse. This is known as an acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. The idle condition is where the device
monitors the SDA and SCL lines waiting for the start condi-
tion and the correct transmitted address. The R/W bit determines
the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7194 acts as a standard slave device on the bus. The data
on the SDA pin is 8 bits long supporting the 7-bit addresses plus
the R/W bit. It interprets the first byte as the device address and
the second byte as the starting subaddress. The subaddresses
autoincrement allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
stop condition. The user can also access any unique subaddress
register on a one by one basis without having to update all the
registers. There is one exception. The Subcarrier Frequency
Registers should be updated in sequence, starting with Sub-
carrier Frequency Register 0. The autoincrement function should
be then used to increment and access Subcarrier Frequency
Registers 1, 2, and 3. The Subcarrier Frequency Registers
should not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period the user should only issue one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7194 will not issue an acknowledge and will return to the
idle condition. If in autoincrement mode, the user exceeds the
highest subaddress then the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is where the SDA line is not
pulled low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7194 and the part will return to the
idle condition.
SDATA
SCLOCK S 1 7 8 9
17 8 9
START ADDR R/W ACK SUBADDRESS ACK
17 8 9
P
DATA ACK STOP
Figure 52. Bus Data Transfer
Figure 52 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 53 shows bus write and read sequences.
WRITE
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
DATA
A(S)
LSB = 1
DATA
A(S) P
READ
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
A(M)
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
DATA
Figure 53. Write and Read Sequences
A(M) P
–28–
REV. 0
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