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ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices

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Description
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ADV7194KST Datasheet PDF : 69 Pages
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ADV7194
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 55 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
Output Video Standard Selection (MR00–MR01)
These bits are used to setup the encoder mode. The ADV7194
can be set up to output NTSC, PAL (B, D, G, H, I), or PAL N
standard video.
Luminance Filter Select (MR02–MR04)
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
Chrominance Filter Select (MR05–MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,
1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or
QCIF filters.
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 56 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC Control (MR10–MR15)
Bits MR15–MR10 can be used to power down the DACs. This are
used to reduce the power consumption of the ADV7194 or if any
of the DACs are not required in the application.
4؋ Oversampling Control (MR16)
To enable 4× Oversampling this bit has to be set to 1. When
enabled, the data is output at a frequency of 54 MHz.
Note that PLL Enable Control has to be enabled (MR61 = 0) in
4× Oversampling mode.
Reserved (MR17)
A Logical 0 must be written to this bit.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
CHROMA FILTER SELECT
MR07 MR06 MR05
0 0 0 1.3 MHz LOW-PASS FILTER
0 0 1 0.65 MHz LOW-PASS FILTER
0 1 0 1.0 MHz LOW-PASS FILTER
0 1 1 2.0 MHz LOW-PASS FILTER
1 0 0 RESERVED
1 0 1 CIF
1 1 0 QCIF
1 1 1 3.0 MHz LOW-PASS FILTER
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0 0 NTSC
0 1 PAL (B, D, G, H, I)
1 0 RESERVED
1 1 PAL (N)
LUMA FILTER SELECT
MR04 MR03 MR02
0 0 0 LOW-PASS FILTER (NTSC)
0 0 1 LOW-PASS FILTER (PAL)
0 1 0 NOTCH FILTER (NTSC)
0 1 1 NOTCH FILTER (PAL)
1 0 0 EXTENDED MODE
1 0 1 CIF
1 1 0 QCIF
1 1 1 RESERVED
Figure 55. Mode Register 0, MR0
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
MR17
ZERO MUST
BE WRITTEN
TO THIS BIT
DAC A
DAC CONTROL
MR15
0 POWER-DOWN
1 NORMAL
DAC C
DAC CONTROL
MR13
0 POWER-DOWN
1 NORMAL
DAC E
DAC CONTROL
MR11
0 POWER-DOWN
1 NORMAL
4؋ OVERSAMPLING
CONTROL
MR16
0 2؋ OVERSAMPLING
1 4؋ OVERSAMPLING
DAC B
DAC CONTROL
MR14
0 POWER-DOWN
1 NORMAL
DAC D
DAC CONTROL
MR12
0 POWER-DOWN
1 NORMAL
DAC F
DAC CONTROL
MR10
0 POWER-DOWN
1 NORMAL
Figure 56. Mode Register 1, MR1
–30–
REV. 0

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