ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7194KST Datasheet PDF : 69 Pages
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ADV7194
Mode 0 (CCIR–656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7194 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing
information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. Mode 0 is illustrated in Figure 38. The HSYNC, VSYNC and BLANK (if not used) pins
should be tied high during this mode. Blank output is available.
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
EAV CODE
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
4 CLOCK
0 F FAAA
0 F FBBB
ANCILLARY DATA
(HANC)
268 CLOCK
SAV CODE
8
0
1
0
8
0
1
0
F
F
0
0
0
0
XC
Yb
Y
C
r
Y
C
b
Y
C
r
Y
C
b
4 CLOCK
1440 CLOCK
4 CLOCK
END OF ACTIVE
VIDEO LINE
280 CLOCK
4 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
Figure 38. Timing Mode 0, Slave Mode
Mode 0 (CCIR–656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7194 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in
the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on
the VSYNC pin. Mode 0 is illustrated in Figure 39 (NTSC) and Figure 40 (PAL). The H, V, and F transitions relative to the video
waveform are illustrated in Figure 41.
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
H
2
3
4
5
6
7
8
9
10
11
V
F
EVEN FIELD ODD FIELD
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
H
V
F
ODD FIELD EVEN FIELD
Figure 39. Timing Mode 0, NTSC Master Mode
283 284 285
–22–
REV. 0
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