ADV7194KST(Rev0) View Datasheet(PDF) - Analog Devices
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Description
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ADV7194KST Datasheet PDF : 69 Pages
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ADV7194
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7194 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when
HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the
ADV7194 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge follow-
ing the timing signal transitions. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL). Figure 44 illustrates the HSYNC,
BLANK and FIELD for an odd-or-even field transition relative to the pixel data.
HSYNC
FIELD
BLANK
PAL = 12 ؋ CLOCK/2
NTSC = 16 ؋ CLOCK/2
PIXEL
DATA
PAL = 132 ؋ CLOCK/2
NTSC = 122 ؋ CLOCK/2
Cb Y Cr Y
Figure 44. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7194 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7194 automatically blanks all normally blank lines as per
CCIR-624. Mode 2 is illustrated in Figure 45 (NTSC) and Figure 46 (PAL).
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
2
3
4
5
6
7
8
9
10
11
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
HSYNC
BLANK
VSYNC
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
ODD FIELD
EVEN FIELD
Figure 45. Timing Mode 2, NTSC
283 284 285
REV. 0
–25–
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