PIC18F010/020
COMF
Complement f
Syntax:
[ label ] COMF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
( f ) → dest
Status Affected: N,Z
Encoding:
0001 11da ffff ffff
Description:
The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in WREG. If ’d’ is 1 the result
is stored back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ’f’
Q3
Process
Data
Q4
Write to
destination
Example:
COMF REG
Before Instruction
REG = 0x13
N
=?
Z
=?
After Instruction
REG =
WREG =
N
=
Z
=
0x13
0xEC
1
0
CPFSEQ
Compare f with WREG,
skip if f = WREG
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0110 001a ffff ffff
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned
subtraction.
If 'f' = WREG, then the fetched
instruction is discarded and an NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ’f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG
:
:
Before Instruction
PC Address =
WREG
=
REG
=
After Instruction
If REG
=
PC
=
If REG
≠
PC
=
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
DS41142A-page 112
Preliminary
2001 Microchip Technology Inc.