PIC16LC925T-I/CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC925T-I/CL

64/68-Pin CMOS Microcontrollers with LCD Driver

Microchip Technology 

PIC16C925/926

FIGURE 15-16: A/D CONVERSION TIMING

BSF ADCON0, GO

Q4

A/D CLK 132

A/D DATA

134

9

ADRES

ADIF

GO

SAMPLE

133

131

130

8

7

...

...

2

OLD_DATA

1

0

NEW_DATA

SAMPLING STOPPED

DONE

133

TABLE 15-12: A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

130 TAD A/D clock period PIC16C925/926

1.6

PIC16LC925/926

3.0

PIC16C925/926

2.0

PIC16LC925/926

3.0

131 TCNV Conversion time (not including S/H time) —

(Note 1)

132 TACQ Acquisition time

(Note 2)

Typ†

—

—

4.0

6.0

—

40

Max Units

Conditions

—

µs TOSC based, VREF ≥ 3.0V

—

µs TOSC based, VREF ≥ 2.0V

6.0

µs A/D RC Mode

9.0

µs A/D RC Mode

12

TAD

—

µs

10

—

—

µs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

5 mV @ 5.12V) from the last sam-

pled voltage (as stated on CHOLD).

134 TGO Q4 to A/D clock start

—

TOSC/2

—

— If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

135 TSWC Switching from convert → sample time

1.5

—

—

TAD

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 10.1 for min. conditions.

DS39544A-page 158

Preliminary

 2001 Microchip Technology Inc.

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