PIC16C925/926
REGISTER 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
R/W-0
U-0
ADFM
—
—
—
bit 7
R/W-0
PCFG3
R/W-0
PCFG2
R/W-0
PCFG1
R/W-0
PCFG0
bit 0
bit 7
bit 6-4
bit 3-0
ADFM: A/D Result Format Select bit
1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.
0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
Unimplemented: Read as '0'
PCFG<3:0>: A/D Port Configuration Control bits:
PCFG<3:0>
AN4
RA5
AN3
RA3
AN2
RA2
AN1
RA1
AN0
RA0
VREF+
VREF-
CHAN/
Refs(1)
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
A VREF+ A
A
A
A
A
A
A VREF+ A
A
D
A
D
A
D VREF+ D
A
D
D
D
D
A VREF+ VREF- A
A
A
A
A
A VREF+ A
A
A VREF+ VREF- A
A VREF+ VREF- A
D VREF+ VREF- A
D
D
D
D
D VREF+ VREF- D
A
VDD
VSS
5/0
A
RA3 VSS
4/1
A
VDD
VSS
5/0
A
RA3 VSS
4/1
A
VDD
VSS
3/0
A
RA3 VSS
2/1
D
VDD
VSS
0/0
A RA3 RA2 3/2
A
VDD
VSS
5/0
A
RA3 VSS
4/1
A RA3 RA2 3/2
A RA3 RA2 3/2
A RA3 RA2 2/2
A
VDD
VSS
1/0
A RA3 RA2 1/2
A = Analog input D = Digital I/O
Note 1: This column indicates the number of analog channels available as A/D inputs and
the number of analog channels used as voltage reference inputs.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
The ADRESH:ADRESL registers contain the 10-bit
result of the A/D conversion. When the A/D conversion
is complete, the result is loaded into this A/D result reg-
ister pair, the GO/DONE bit (ADCON0<2>) is cleared
and the A/D interrupt flag bit ADIF is set. The block dia-
gram of the A/D module is shown in Figure 10-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 10.1. After this
acquisition time has elapsed, the A/D conversion can
be started.
DS39544A-page 76
Preliminary
2001 Microchip Technology Inc.