PIC16LC926-I/PT View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC926-I/PT

64/68-Pin CMOS Microcontrollers with LCD Driver

Microchip Technology 

PIC16C925/926

10.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 10-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD), see Figure 10-2. The maximum recom-

mended impedance for analog sources is 10 kΩ. As

the impedance is decreased, the acquisition time may

EQUATION 10-1: ACQUISITION TIME EXAMPLE

TACQ =

=

=

TC =

=

=

TACQ =

=

Amplifier Settling Time +

Hold Capacitor Charging Time +

Temperature Coefficient

TAMP + TC + TCOFF

2µS + TC + [(Temperature -25°C)(0.05µS/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)

16.47µS

2µS + 16.47µS + [(50°C -25°C)(0.05µS/°C)

19.72µS

be decreased. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time,

Equation 10-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range Reference Manual

(DS33023).

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leak-

age specification.

4: After a conversion has completed, a 2.0TAD delay must complete before acquisition can begin again.

During this time, the holding capacitor is not connected to the selected A/D input channel.

FIGURE 10-2:

ANALOG INPUT MODEL

RS ANx

VDD

VT = 0.6V

VA

CPIN

5 pF

VT = 0.6V

Sampling

Switch

RIC ≤ 1k SS RSS

I LEAKAGE

± 500 nA

CHOLD

= DAC Capacitance

= 120 pF

VSS

Legend

CPIN

= input capacitance

VT

= threshold voltage

I LEAKAGE = leakage current at the pin due to

various junctions

RIC

= interconnect resistance

SS

= sampling switch

CHOLD = sample/hold capacitance (from DAC)

6V

5V

VDD 4V

3V

2V

5 6 7 8 9 10 11

Sampling Switch

(kΩ)

DS39544A-page 78

Preliminary

 2001 Microchip Technology Inc.

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