ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
11.7.5 Low Power Modes
Mode
WAIT
HALT
Description
No effect on I2C interface.
I2C interrupts cause the device to exit from WAIT mode.
I2C registers are frozen.
In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface
resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability.
11.7.6 Interrupts
Figure 69. Event Flags and Interrupt Generation
ITE
BTF
SB
AF
INTERRUPT
*
EVF
* EVF *can also be set by EV2 or an error from the SR2 register.
Interrupt Event
End of Byte Transfer Event
Start Bit Generation Event (Master mode)
Acknowledge Failure Event
Note: The I2C interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the I-bits in the CC
register are reset (RIM instruction).
Event
Flag
BTF
SB
AF
Enable
Control
Bit
ITE
Exit
from
Wait
Yes
Yes
Yes
Exit
from
Halt
No
No
No
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