ST72652 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72652 Datasheet PDF : 166 Pages
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ST7265x
I²C SINGLE MASTER BUS INTERFACE (Cont’d)
I2C STATUS REGISTER 2 (SR2)
Read Only
Reset Value: 0000 0000 (00h)
7
0
0
0
0
AF
0
0
0
0
Bit 7:5 = Reserved. Forced to 0 by hardware.
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge
is returned. An interrupt is generated if ITE=1. It is
cleared by software reading SR2 register or by
hardware when the interface is disabled (PE=0).
The SCL line is not held low while AF=1.
0: No acknowledge failure
1: Acknowledge failure
Bit 3:0 = Reserved. Forced to 0 by hardware.
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