STLC1502 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

STLC1502

6.5.3 Transfer interrupts

The DMA_MAC can interrupt the CPU with three different levels of information about transfer completion.

The CPU can choose which interrupt needs to be enabled. They do not exclude each other though; they

can be all three enabled at the same time.

The TX_CURR_DONE (RX_CURR_DONE) interrupt bit reports the CPU when a single Descriptor (i.e.

one frame) has been completely treated by the DMA_MAC and the CPU is again the owner (VALID bit

set to 0).

The TX_NEXT (RX_NEXT) interrupt bit is set when next descriptor fetch is enabled (NXT_EN=1 in the

current descriptor) the next Descriptor is not valid (VALID bit is off).

The TX_DONE (RX_DONE) interrupt bit is set when a whole DMA transfer is complete. This can happen

either when the current is the last Descriptor in the chain (NXT_EN is off) or when the next Descriptor is

not valid yet (VALID bit is off) and the polling is disabled (NPOL_EN bit is off).

6.5.4 Frames transmission (TX)

When the CPU wants to transmit a set of frames on the cable, it needs to provide the DMA_MAC with a

Descriptor list. The CPU is expected to allocate a Descriptor for each frame it wants to send, to fill it with

the DMA control information and the pointer to the frame, and to link the Descriptor in the chain. The

frames will be sent on the cable in the same order they are found in the chain.

6.5.6 Open list approach

The simplest way to construct a Descriptor chain is the open list approach. Every Descriptor but the last

one will have the DMA_Next field pointing to the next Descriptor in the chain, the NXT_EN bit and the

VALID bit on, the NPOL_EN bit on/off. The last Descriptor will be set in the same way except for the

NXT_EN bit (off) and the DMA_Next field (NULL).

• The CPU starts the DMA activity loading the physical location of the first Descriptor into the DMA

Next register of the DMA_MAC and set the DMA Start register enable bit to on.

• The DMA_MAC will then keep fetching the Descriptors one by one until it finds the NXT_EN bit of the

last Descriptor set to off. Every time it completes a Descriptor (frame) it saves the transfer status into

TxRx_Status, it turns the Descriptor VALID bit to off and raises the TX_CURR_DONE interrupt bit.

• When the NXT_EN bit is found to be off, that means the DMA_MAC has fetched the last Descriptor in

the chain. When it completes also this Descriptor (the end of the DMA transfer) it raises both the

TX_CURR_DONE and the TX_DONE interrupt bits.

6.5.7 Closed list approach

The approach above is easy since it doesn’t require the DMA_MAC and the CPU to synchronize their ac-

cess to the Descriptor chain. The problem is that it requires the CPU to build the list every time it needs a

transfer.

A faster way to operate is building a closed Descriptor list only the first time and using the VALID bit to

mark the end of the transfer. The polling facility could also be used to save the CPU from the activity of

programming the DMA Start register every time it needs to start the DMA transfer. Instead, the DMA Start

register will be activated only once and the DMA_MAC will keep polling the invalid descriptor, raising

each time the TX_NEXT interrupt bit (if enabled), until the CPU finally sets its VALID bit to on. Since the

DMA transfer practically never ends, note that in this case the TX_DONE interrupt bit is never raised.

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