STLC1502 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC1502

VOICE OVER IP PROCESSOR

STMicroelectronics 

Address

Register Name

Eth_base2+ 0x013C RX_FIFO_15

Eth_base2+ 0x0180-

Eth_base2+ 0x01FC

Eth_base2+ 0x0200 TX_FIFO_0

....

...

Eth_base2+ 0x023C TX_FIFO_15

Eth_base2+ 0x0280-

Eth_base2+ 0x03FF

Eth_base2+ 0x0400- MAC110

Eth_base2+ 0x07FF

STLC1502

Notes

RX FIFO 32 bit word #15

Reserved

TX FIFO 32 bit word #0

...

TX FIFO 32 bit word #15

Reserved

Refer to the InSilicon MAC110 specifica-

tion (see Ref. [2])

6.6 Arbiter

The arbiter is used to ensure that, at any point in time, only one master has access to the bus. It performs this

function by observing all of the bus master requests to use the bus, and deciding which is currently the highest

priority. It has a standard interface to all bus masters and split-capable slaves in the system. However it does

not support SPLIT bus transfers.

A bus master may request the bus during any cycle by setting its HBUSREQ output HIGH. This is then sampled

by the arbiter on the rising edge of the clock, and passed through the priority algorithm to decide which master

will have access to the bus during the next cycle. The HGRANT then outputs change to indicate which master

currently is granted control of the bus.

The HLOCK signals may be used to ensure that during an indivisible transfer, the current grant outputs do not

change. HLOCK must be asserted at least one cycle before the locked transfer to prevent the arbiter from

changing the grant signals. When more than one master requests ownership of the system bus, the priority used

for arbitration is:

• Highest: TIC

• Printer Drive Control

• DMA Controller

• Lowest: ARM7TDMI (default master)

The ARM7TDMI will periodically assume top priority on the system bus: this period can be programmed. Also,

it will assume top priority when an interrupt occurs, if the interrupt mode is enabled. During reset, and when no

other masters are requesting control of the bus, the ARM7TDMI is selected as the currently granted master.

This minimizes the delay required for the core to perform a transfer on the bus, as it does not have to wait to be

granted control of the bus before it can start a new transfer.

The system also requires a default master, which is selected when no masters are granted control of the bus,

for example, when all system bus masters are waiting for split transfers to complete. The default master per-

forms IDLE transfers while it is granted control of the bus. The bus grant outputs may change while HREADY

is LOW, but the newly granted master may only drive the bus when the current transfer has completed. This

requires that bus masters only drive the bus after they detect that both their HGRANT and HREADY inputs are

set HIGH.

All registers used in the system are clocked from the rising edge of the system clock HCLK, and use the asyn-

chronous reset HRESETn. The arbiter control and status registers are accessed via the APB bus.

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