STPCI2 View Datasheet(PDF) - STMicroelectronics
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STPCI2 Datasheet PDF : 108 Pages
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STPC® ATLAS
6.6.3.3. POST code
Once the 16 first bytes are fetched and decoded,
the CPU core continue its execution depending on
the content of these first data. Usually, it
corresponds to a JUMP instruction and the code
fetching continues, generating read cycles on the
ISA bus.
previous steps has not been done properly, like
HCLK speed and CPU clock multiplier (x1, x2).
6.6.4.2. Boot Flash size
The Local Bus support 8-bit and 16-bit boot
memory devices only.
6.6.4.3. POST code
Most of the BIOS and boot loaders are reading the
content of the flash, decompressing it in SDRAM,
and then continue the execution by jumping to the
entry point in RAM. This boot process ends with a
JUMP to the entry point of the OS launcher.
These various steps of the booting sequence are
Like in ISA mode, POST codes can be
implemented on the Local Bus. The difference is
that an IOCS# must be programmed at I/O
address 80H prior to writing these code, the POST
display being connected to this IOCS# and to the
lower 8 bits of the bus.
codified by the so-called POST codes (Power-On
Self-Test). A 8-bit code is written to the port 80H at 6.6.5. SUMMARY
the beginning of each stage of the booting process
(I/O write to address 0080H) and can be displayed Here is a check-list for the STPC board debug
on two 7-segment display, enabling a fast visual
check of the booting completion level.
) Usually, the last POST code is 0x00 and
t(s corresponds to the jump into the OS launcher.
c When the execution fails or hangs, the lastest
u written code stays visible on that display,
d indicating either the piece of code to analyse,
ro either the area of the hardware not working
P properly.
te 6.6.4. LOCAL BUS MODE
ole As the Local Bus controller is located into the Host
s interface, there is no access to the cycles on the
b PCI, reducing the amount of signals to check.
O 6.6.4.1. First code fetches
- When booting on the Local Bus, the key signal to
) check at the very beginning is FCS0#. This signal
t(s is a Chip Select for the boot flash and should
c toggle together with PRD# to fetch the first 16
u bytes of code. This corresponds to the loading of
d the first line of the CPU cache.
ro In case FCS0# does not toggle, then one of the
from power-on to CPU execution.
For each step, in case of failure, verify first the
corresponding balls of the STPC:
- check if the voltage or activity is correct
- search for potential shortcuts.
For troubleshooting in steps 5 to 10, verify the
related strap options:
- value & connection. Refer to Section 3.
- see Figure 4-3 for timing constraints
Steps 8a and 9a are for debug in ISA mode while
steps 8b and 9b are for Local Bus mode.
6.6.6. PCMCIA mode
As the STPC uses the RMRTCCS# signal for
booting in that mode, the methodology is the same
as for the ISA bus. The PCMCIA cards being 3.3V
or 5V, the boot flash device must be 5V tolerant
when directly connected on the address and data
busses. An other solution is to isolate the flash
from the PCMCIA lines using 5V tolerant LVTTL
buffers.
P Check:
How?
lete Verify that voltage is within specs:
so 1
Power
supplies
- this must include HF & LF noise
- avoid full range sweep
Ob Refer to Table 4-1 for values
Troubleshooting
Measure voltage near STPC balls:
- use very low GND connection.
Add some decoupling capacitor:
- the smallest, the nearest to STPC balls.
The 2 capacitors used with the quartz must
2 14.318 MHz Verify OSC14M speed
match with the capacitance of the crystal.
Try other values.
3
SYSRSTI# Measure SYSRSTI# of STPC
(Power Good) See Figure 4-3 for waveforms.
Verify reset generation circuit:
- device reference
- components value
105/108
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