STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

6.4.3. MEMORY INTERFACE

6.4.3.1. Introduction

In order to achieve SDRAM memory interfaces

which work at clock frequencies of 90 MHz and

above, careful consideration has to be given to the

timing of the interface with all the various electrical

and physical constraints taken into consideration.

The guidelines described below are related to

SDRAM components on DIMM modules. For

applications where the memories are directly

soldered to the motherboard, the PCB should be

laid out such that the trace lengths fit within the

constraints shown here. The traces could be

slightly shorter since the extra routing on the

DIMM PCB is no longer present but it is then up to

the user to verify the timings.

6.4.3.2. SDRAM Clocking Scheme

The SDRAM Clocking Scheme deserves a special

mention here. Basically the memory clock is

generated on-chip through a PLL and goes directly

to the MCLKO output pin of the STPC. The

nominal frequency is 90 MHz. Because of the high

load presented to the MCLK on the board by the

DIMMs it is recommended to rebuffer the MCLKO

signal on the board and balance the skew to the

clock ports of the different DIMMs and the MCLKI

input pin of STPC.

Figure 6-21. Clock Scheme

duct(s) PLL

MCLKO

solete Pro PLL

t(s) - Ob SDRAM

uc CONTROLLER

MCLKI

MA[ ] + Control

MD[63:0]

olete Prod 6.4.3.3. Board Layout Issues

bs The physical layout of the motherboard PCB

Oassumed in this presentation is as shown in Figure

reduce EMI and noise. Also there should be ample

high frequency decoupling between the power and

ground planes to provide a low impedance path

between the planes for the return paths for signal

6-22. Because all of the memory interface signal routings which change layers. If possible, the

balls are located in the same region of the STPC traces should be routed adjacent to the same

device, it is possible to orientate the device to power or ground plane for the length of the trace.

reduce the trace lengths. The worst case routing

length to the DIMM1 is estimated to be 100 mm.

Solid power and ground planes are a must in order For the SDRAM interface, the most critical signal

to provide good return paths for the signals and to is the clock. Any skew between the clocks at the

91/108

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