STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

6.5.1. PCI INTERFACE

6.5.1.3. Board Layout Issues

6.5.1.1. Introduction

The physical layout of the motherboard PCB

assumed in this presentation is as shown in Figure

In order to achieve a PCI interface which work at 6-29. For the PCI interface, the most critical signal

clock frequencies up to 33MHz, careful is the clock. Any skew between the clocks at the

consideration has to be given to the timing of the PCI components and the STPC will impact the

interface with all the various electrical and physical timing budget. In order to get well matched clocks

constraints taken into consideration.

at all components it is recommended that all the

PCI clocks are individually driven from a serial

6.5.1.2. PCI Clocking Scheme

resistance with matched routing lengths. In other

words, all clock line lengths that go from the

The PCI Clocking Scheme deserves a special resistor to the PCI chips (PCICLKx) must be

mention here. Basically the PCI clock (PCICLKO) identical.

is generated on-chip from HCLK through a

programmable delay line and a clock divider. The The figure below is for PCI devices soldered on-

nominal frequency is 33MHz. This clock must be board. In the case of a PCI slot, the wire length

looped to PCICLKI and goes to the internal South must be shortened by 2.5" to compensate the

Bridge through a deskewer. On the contrary, the

internal North Bridge is clocked by HCLK, putting

Obsolete Product(s) - Obsolete Product(s) some additionnal constraints on T0 and T1.

clock layout on the PCI board. The maximum clock

skew between all devices is 2ns according to PCI

specifications.

The Figure 6-30 describes a typical clock delay

implementation. The exact timing constraints are

listed in the PCI section of the Electrical

Specifications Chapter.

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