STPCI2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

Table 4-14. ISA Bus AC Timing

Name Parameter

Min

Max

Units

10c Memory access to 16-bit ISA Slave

2T

Cycle

10d Memory access to 8-bit ISA Slave

2T

Cycle

10e

SA[19:0] & SBHE valid before IOR#, IOW# asserted

2T

Cycles

11

ISACLK2X to IOW# valid

11a Memory access to 16-bit ISA Slave - 2BCLK

2T

Cycles

11b Memory access to 16-bit ISA Slave - Standard 3BCLK

2T

Cycles

11c Memory access to 16-bit ISA Slave - 4BCLK

2T

Cycles

11d Memory access to 8-bit ISA Slave - 2BCLK

2T

Cycles

11e

Memory access to 8-bit ISA Slave - Standard 3BCLK

2T

Cycles

12

ALE# asserted before ALE# negated

1T

Cycles

13

ALE# asserted before MEMR#, MEMW# asserted

13a Memory Access to 16-bit ISA Slave

2T

Cycles

13b Memory Access to 8-bit ISA Slave

2T

13

ALE# asserted before SMEMR#, SMEMW# asserted

) 13c Memory Access to 16-bit ISA Slave

2T

t(s 13d Memory Access to 8-bit ISA Slave

2T

c 13e

ALE# asserted before IOR#, IOW# asserted

2T

u 14

ALE# asserted before AL[23:17]

rod 14a Non compressed

15T

14b Compressed

15T

P 15

ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated

te 15a Memory Access to 16-bit ISA Slave- 4 BCLK

11T

le 15e Memory Access to 8-bit ISA Slave- Standard Cycle

11T

o 18a

ALE# negated before LA[23:17] invalid (non compressed)

14T

s 18a

ALE# negated before LA[23:17] invalid (compressed)

14T

b 22

MEMR#, MEMW# asserted before LA[23:17]

O 22a Memory access to 16-bit ISA Slave.

13T

) - 22b Memory access to 8-bit ISA Slave.

13T

t(s 23

MEMR#, MEMW# asserted before MEMR#, MEMW# negated

23b Memory access to 16-bit ISA Slave Standard cycle

9T

uc 23e Memory access to 8-bit ISA Slave Standard cycle

9T

d 23

SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated

ro 23h Memory access to 16-bit ISA Slave Standard cycle

9T

P 23l Memory access to 16-bit ISA Slave Standard cycle

9T

23

IOR#, IOW# asserted before IOR#, IOW# negated

te23o Memory access to 16-bit ISA Slave Standard cycle

9T

le 23r Memory access to 8-bit ISA Slave Standard cycle

9T

so24

MEMR#, MEMW# asserted before SA[19:0]

b 24b Memory access to 16-bit ISA Slave Standard cycle

10T

O 24d Memory access to 8-bit ISA Slave - 3BLCK

10T

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

Cycles

24e Memory access to 8-bit ISA Slave Standard cycle

10T

Cycles

24f Memory access to 8-bit ISA Slave - 7BCLK

10T

Cycles

24

SMEMR#, SMEMW# asserted before SA[19:0]

24h Memory access to 16-bit ISA Slave Standard cycle

10T

Cycles

Note: The signal numbering refers to Figure 4-8

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