STPCD01 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCD01

PC Compatible Embedded Microprocessor

STMicroelectronics 

UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

2.3 UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

The following changes have been made to the Pin Description Chapter on 08/02/2000

Section Change

2.2.3. Replaced

Text

Signals VIDEO_D[7:0] with VIN, VTV_BT# with ODD_EVEN, VTV_SYNCH with VCS.

The following changes have been made to the Pin Description Chapter on 13/01/2000

Section Change

2.2.

Added

Text

“to a minimum of 8MHz”

DCLK Dot Clock / Pixel clock. This clock supplies the display controller, the video pipeline, the ramdac,

and the TV output logic. Its value is dependent on the selected display mode.

Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of

8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register

bit.

The following changes have been made to the Pin Description Chapter on 28/09/99

Section Change

Table 2-1. Changed

Figure 2-1. Changed

Table 2-2. Replaced

2.2.1. Moved

2.2.1. Moved

2.2.3. Replaced

Text

Updated signal pin counts and added abbreviations to table.

Updated External interface pin count

“PWGD” with “SYSRSTI#”

PCI_CLKI and PCI_CLKO moved from 2.2.1. to 2.2.5.

ISA_CLK and ISA_CLKX2 moved from 2.2.1. to 2.2.8.

“Video Interface” with “Video Input”

The following changes have been made to the Pin Description Chapter on 23/09/99

Section Change

2.2.13. Added

Text

“Note;

By setting signals ST[3:0] to the following value allows the STPC to be put

Tristate. This means the STPC is switched off and no signals are being driven.“

The following changes have been made to the Pin Description Chapter on 11/08/99

Removed statement; “The direction can be controlled by a strap option or an internal register bit.”

Issue 1.7 - February 8, 2000

25/48

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