STPCD01 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STPCD01 Datasheet PDF : 48 Pages
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UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER
The following changes have been made to the Pin Description Chapter from Revision 1.0 to Release 1.2.
Section Change
2.1.
Replaced
2.2.1. Replaced
2.2.1. Replaced
2.2.6. Replaced
2.2.6. Replaced
2.2.8. Replaced
2.2.12.
2.2.12.
Added
Replaced
Text
“internal” With “assimilated “
“The DRAM controller to execute the host transactions is also driven by this
clock”
With
“This clock drives the DRAM controller to execute the host transactions”
“AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data
bus of the PCI. This bus is driven by the master during the address phase and
data phase of write transactions. It is driven by the target during data phase of
read transactions.”
With
“AD[31:0] PCI Address/Data. This is the 32-bit PCI multiplexed address and
data bus. This bus is driven by the master during the address phase and data
phase of write transactions. It is driven by the target during data phase of read
transactions.”
“IDE devices are connected to SA[19:8] directly and ISA bus is connected to
these pins through two LS245 transceivers. The OE of the transceivers are
connected to ISAOE# and the DIR is connected to MASTER#. The A bus sig-
nals of the transceivers are connected to CPC and IDE DD bus and the B bus
signals are connected to ISA SA bus.”
With
“IDE devices are connected to SA[19:8] directly and the ISA bus is connected
to these pins through two LS245 transceivers. The transceiver OEs are con-
nected to ISAOE# and the DIR is connected to MASTER#. The transceiver bus
signals are connected to the CPC and IDE DD busses and B bus signals are
connected to ISA SA bus.”
“For IDE devices, these signals are used as the DA[2:0] and are connected to
DA[2:0] of IDE devices directly or through a buffer. If the toggling of signals is to
be masked during ISA bus cycles, they can be externally ORed before being
connected to the IDE devices.”
With
“For IDE devices, these signals are used as the DA[2:0] and are connected di-
rectly or through a buffer to DA[2:0] of the IDE devices. If the toggling of signals
are to be masked during ISA bus cycles, they can be externally ORed before
being connected to the IDE devices.”
“IOCS16# IO Chip Select16. This signal is the decode of the ISA bus SA15-0
address pins of without any qualification of the command signals. The STPC
Client does not drive IOCS16# (similar to PC-AT design). An ISA master ac-
cess to an internal register of the STPC Client is executed as an extended 8-bit
IO cycle.”
With
“IOCS16# IO Chip Select16. This signal is the decode of SA15-0 address pins
of the ISA address bus without any qualification of the command signals. The
STPC Client does not drive IOCS16# (similar to PC-AT design). An ISA master
access to an internal register of the STPC Client is executed as an extended 8-
bit IO cycle.”
“They can instead be used for accessing I C devices on board. DDC1 and
DDC0 correspond to SCL and SDA respectively.”
Updated table 3
26/48
Issue 1.7 - February 8, 2000
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