STPCC0166BTC3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCC0166BTC3

PC Compatible Embeded Microprocessor

STMicroelectronics 

STRAP OPTION

Memory

Data Note

Lines

MD38

MD39

MD40

MD41

MD42

MD43

Refer to

-

-

CPU

-

-

-

Designation

Reserved

Reserved

CPU Mode

Reserved

Reserved

Reserved

Note;

1) This Strap Option selects between two different

functional blocks, the first is the ISA (SMEMW#)

and the other is the VGA block (Color_Key).

2) Setting of Strap Options MD [2:15] have no ef-

fect on the DRAM Controller but are purely meant

for software issues. i.e. Readable in a register.

3.1 STRAP REGISTER DESCRIPTION

3.1.1 STRAP REGISTER 0 INDEX 4AH

(STRAP0)

Bits 7-0 of this register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Bit Sampled

Bit 7

Bits 6-5

Bit 4

Bits 3-2

Bits 1-0

Description

SIMM 0 dram type

SIMM 0 speed

SIMM 1 dram type

SIMM 1 speed

Reserved

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[7:0] pins after reset.

Location

-

-

-

-

-

Actual

Settings

Set to ’0’

Pull up

Pull up

User defined

Pull down

Pull up

Pull down

-

-

DX1

-

-

-

Set to ’1’

-

-

DX2

-

-

-

3.1.2 STRAP REGISTER 1 INDEX 4BH

(STRAP1)

Bits 7-0 of this register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Bit Sampled

Bit 7

Bits 6-5

Bit 4

Bits 3-2

Description

SIMM 2 dram type

SIMM 2 speed

SIMM 3 dram type

SIMM 3 speed

Note that the SIMM speed and type information

read here is meant only for thesoftware and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[15:8] pins after reset.

3.1.3 STRAP REGISTER 2 INDEX 4CH

(STRAP2)

Bits 4-0 of this register reflect the status of pins

MD[20:16] respectively. Bit 5 of this register reflect

the status of pin MD[23]. Bit 4 is writeable, writes

to other bits in this register have no effect.

They are use by the chip as follows:

Bit 4-2; Reserved

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Issue 1.2

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