STPCC0166BTC3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STPCC0166BTC3

PC Compatible Embeded Microprocessor

STMicroelectronics 

Bit 1 This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

0: PCI clock output = HCLK / 2

1: PCI clock output = HCLK / 3

Bit 0; Reserved

This register defaults to the values sampled on

MD[23] & MD[20:16] pins after reset.

3.1.4 HCLK PLL STRAP REGISTER 0 INDEX

5FH (HCLK_STRAP0)

Bits 5-0 of this register reflect the status of pins

MD[26:21] respectively. They are use by the chip

as follows:

STRAP OPTION

Bits 5-3; These pins reflect the value sampled on

MD[26:24] pins respectively and control the Host

clock frequency synthesizer.

Bit 2-0; Reserved

This register defaults to the values sampled on

above pins after reset.

Strap Options [39:27] are reserved.

3.1.5 486 CLOCK PROGRAMMING (486_CLK)

The bit MD[40] is used to set the clock multiplica-

tion factor of the 486 core. With the MD[40] pin

pulled low the 486 will run in DX (x1) mode, while

with the MD[40] pin pulled high the 486 will run in

DX2 (x2) mode. The default value of the resistor

on this strap input should be a resister to ground

(DX mode).

Strap options MD[43:41] are reserved.

Issue 1.2

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