ELECTRICAL SPECIFICATIONS
Figure 4-1 Drive Level and Measurement Points for Switching Characteristics
CLK:
OUTPUTS:
B
Valid
Output n
A
MIN
Tx
MAX
VRef
Valid
Output n+1
INPUTS:
C
D
Valid
Inp ut
LEGE ND:
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
Figure 4-2 CLK Timing Measurement Points
VIHD
VRef
VILD
VIHD
VRef
VILD
T1
T2
VIH (MIN)
VRef
CLK VIL (MAX)
T5
T3
T4
LEGE ND:
T1 - One Clock Cycle
T2 - Minimum Time at VIH
T3 - Minimum Time at VIL
T4 - Clock Fall Time
T5 - Clock Rise Time
NOTE; All sIgnals are sampled on the rising edge of the CLK.
Note; The above timings are generic timings and are not specific to the interfaces defined below
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