ELECTRICAL SPECIFICATIONS
Table 4-7. Video Input AC Timing
Name
t35
t36
t37
t38
t39
t40
t41
t42
Parameter
VIN[7:0] setup to VCLK
VIN[7:0] hold from VCLK
VCLK to ODD_EVEN valid
VCLK to VCS valid
ODD_EVEN setup to VCLK
ODD_EVEN hold from VCLK
VCS setup to VCLK
VCS hold from VCLK
Table 4-8. Graphics Adapter (VGA) AC Timing
Name
t43
t44
Parameter
DCLK to VSYNC valid
DCLK to HSYNC valid
Table 4-9. ISA Bus AC Timing
Name
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
Parameter
XTALO to LA[23:17] bus active
XTALO to SA[19:0] bus active
XTALO to BHE# valid
XTALO to SD[15:0] bus active
PCI_CLKI to ISAOE# valid
XTALO to GPIOCS# valid
XTALO to ALE valid
XTALO to MEMW# valid
XTALO to MEMR# valid
XTALO to SMEMW# valid
XTALO to SMEMR# valid
XTALO to IOR# valid
XTALO to IOW# valid
Min
Max
Unit
5
ns
4
ns
15
ns
15
ns
10
ns
5
ns
10
ns
5
ns
Min
Max
Unit
30
ns
30
ns
Min
Max
Unit
60
ns
60
ns
62
ns
35
ns
28
ns
60
ns
62
ns
50
ns
50
ns
50
ns
50
ns
50
ns
50
ns
34/51
Issue 1.2