STPCC4HEBI View Datasheet(PDF) - STMicroelectronics
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STPCC4HEBI Datasheet PDF : 93 Pages
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DESIGN GUIDELINES
6.3.10. TV INTERFACE
The STPC integrates a voltage reference and
video DACs. The amount of external devices is
then limited to video buffers as described in the
Figure 6-15.
The connection from IREFx and VREFx up to the
20 ohms resistors must be as short as possible.
The constraint is the same for the connection from
Figure 6-15. Typical VGA implementation
VDDA_TV and VSSA_TV up to the decoupling
capacitances.
The resistors and capacitors of the amplifier stage
have to be as close as possible to the video buffer.
When the TV interface is not needed, the signals
RED, GREEN, BLUE, CVBS, IREF1, IREF2 can
be left unconnected, VDDA_TV must then be
connected to GND.
IREF1
VREF1
IREF2
VREF2
VDDA_TV
VSSA_TV
RED
GREEN
BLUE
CVBS
20 1%
AGND
AGND
Rref = 20K 1%
VCCA
5V
FBEAD
2.5V
FBEAD
AGND
100nF 22uF
FBEAD GND
100nF 22uF
AGND
15uH
AGND
47pF
VCCA
TSH74
AGND
AGND
75 1%
To the connector
same
as for
RED
526
326
1% AGND 1%
478 1%
316 1%
10
1%
10nF
AGND
DCLK
GND
33
27MHz
3.3V
FBEAD
100nF
GND
GND
R,G,B,CVBS outputs:
. Ioutmax = 80.704 / Rref < 5mA
. Rload = 274 ohms
. Vout = {10-bit code} x Rload x 0.079 / Rref
Fine tuning of the maximum output level must be
done using the gain control registers 0x11 to 0x13
of the integrated Digital Encoder (write the value
0x0B for a gain of 109%).
Release 1.5 - January 29, 2002
75/93
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