PIN DESCRIPTION
Signal Name
IDE CONTROL
DA[2:0]
DD[15:12]
DD[11:0]
PCS3#,PCS1#,SCS3#,SCS1#
DIORDY
PIRQ, SIRQ
PDRQ, SDRQ
PDACK#, SDACK#
PDIOR#, SDIOR#
PDIOW#, SDIOW#
Table 2-2. Definition of Signal Pins
Dir
Buffer Type2
Description
Qty
O
BD8STRUP_FT Address Bus
3
I/O
BD4STRP_FT Data Bus
4
I/O
BD8STRUP_FT Data Bus
12
O
BD8STRUP_FT Primary & Secondary Chip Selects
4
O
BD8STRUP_FT Data I/O Ready
1
I
BD4STRP_FT Primary & Secondary Interrupt Request 2
I
BD4STRP_FT Primary & Secondary DMA Request
2
O
BD8STRP_FT
Primary & Secondary DMA
Acknowledge
2
O
BD8STRUP_FT Primary & Secondary I/O Channel Read 2
O
BD8STRP_FT Primary & Secondary I/O Channel Write 2
MISCELLANEOUS
GPIO[15:0]
I/O
BD4STRP_FT General Purpose I/Os
16
SPKRD
O
BD4STRP_FT Speaker Device Output
1
SCL
I/O
BD4STRUP_FT
I²C Interface - Clock / Can be used for
VGA DDC[1] signal
1
SDA
I/O
BD4STRUP_FT
I²C Interface - Data / Can be used for
VGA DDC[0] signal
1
SCAN_ENABLE
I
TLCHTD_TC
Reserved (Test pin)
1
TCLK
I
BD4STRP_FT Test clock
1
TDI
I
BD4STRP_FT Test data input
1
TMS
I
BD4STRP_FT Test mode input
1
TDO
O
BD4STRP_FT Test data output
1
Note1: These pins must be connected to the 2.5 V power supply. They must not be connected to the 3.3V supply.
Note2: See Table 2-3 for buffer type descriptions.
14/87
Release 1.3 - January 29, 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.