CL-PS7500FE View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CL-PS7500FE Datasheet PDF : 251 Pages
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CL-PS7500FE
System-on-a-Chip for Internet Appliance
a Timing is for all PC style I/O chip selects: nCCS, nCDACK, nPCCS1, nPCCS2, nEASCS, and TC.
b Delay includes four MEMCLK cycles.
c Timings refer to where ASTCR bit = 0.
d Timings refer to where ASTCR bit = 1.
e Synchronization penalty is between 0 and 1 I_OCLK cycles.
f Synchronization penalty is between 0 and 2 I_OCLK cycles.
g Delay includes two MEMCLK cycles.
LA[28:0]
MEMCLK
I_OCLK
CLK16
LA[28:0]
IORNW
nPCCS1
nIOW
nBLO
READY
D[31:16]
ta d d 3
tb d 3
tc s l _ p c
tn i o w l
tn o h 2
tn o l 2
tr d s
Upper 16-bits of external data bus valid for 32-bit I/O
td u
td u h
tr d h
ta d d 2
tb d 2
tc s h _ p c
tn i o w h
Figure 22-18. 16-MHz Type D I/O Write Cycle Timing
June 1997
ADVANCE DATA BOOK v2.0
ELECTRICAL SPECIFICATIONS
215
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