CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

4.3 Memory Interface

The memory interface has been designed to allow the performance potential to be realized without incur-

ring high costs in the memory system. Speed-critical control signals are pipelined to allow system control

functions to be implemented in standard low-power logic, and these control signals permit the

CL-PS7500FE to exploit the page mode access offered by industry-standard DRAMs.

4.4 Clocks and Synchronous/Asynchronous Modes

The ARM processor uses two independent clock sources, MCLK and FCLK. Both are generated internally

to the CL-PS7500FE from MEMCLK and CPUCLK. The ARM7 core CPU switches between MCLK and

FCLK according to the operation being carried out. For example, if the ARM7 core CPU is reading data

from the cache, it is clocked by FCLK; if the core CPU is reading data from uncached memory then it is

clocked by MCLK. The control logic of the ARM processor ensures that the correct clock is used internally

and switches between the two clocks automatically.

When SnA is tied high, MEMCLK creates both FCLK and MCLK; MCLK has half the frequency of FCLK.

This synchronous mode ensures that there are no synchronization penalties whenever the ARM 7 core

is switched between FCLK and MCLK.

When SnA is tied low, MEMCLK creates MCLK and CPUCLK must be driven to supply FCLK. MEMCLK

and CPUCLK can be of unrelated frequency. There is a synchronization penalty whenever the ARM7 core

clock switches between MCLK and FCLK. This penalty is symmetric, and varies between nothing and a

whole period of the clock where the core resynchronized. Thus, when changing there is an average resyn-

chronization penalty of one-half a clock period, MCLK or FCLK as appropriate.

A[31:0] NR/W

NB/W

ADDRESS BUFFER

INTERNAL ADDRESS BUS

MCLK SNA FCLK

NRESET

CLOCK

NMREQ

MMU

4-KBYTE

CACHE

ARM7

CPU

CONTROL

NIRQ

NFIQ

WRITE

BUFFER

DBE

D[31:0]

INTERNAL DATA BUS

CONNECTION TO

FPA COPROCESSOR

CONTROL

COPROC

Figure 4-1. ARM Processor Block Diagram

34

THE ARM PROCESSOR MACROCELL

ADVANCE DATA BOOK v2.0

June 1997

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