CL-PS7500FE View Datasheet(PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

6. ARM PROCESSOR MMU

The MMU performs two primary functions: it translates virtual addresses into physical addresses, and it

controls memory access permissions. The MMU hardware required to perform these functions consists

of a TLB, access control logic, and translation table walking logic.

The MMU supports memory accesses based on Sections or Pages:

q Sections are comprised of 1-Mbyte blocks of memory.

q Pages – two different page sizes are supported:

— Small pages consist of 4-Kbyte blocks of memory. Additional access control mechanisms are extended

within small pages to 1-Kbyte subpages.

— Large pages consist of 64-Kbyte blocks of memory. Additional access control mechanisms are extended

within large pages to 16-Kbyte subpages. Large pages are supported to allow mapping of a large region

of memory while using only a single entry in the TLB.

The MMU also supports the concept of domains — areas of memory that can be defined to possess indi-

vidual access rights. The Domain Access Control register specifies access rights for up to 16 separate

domains.

The TLB caches 64 translated entries. During most memory accesses, the TLB provides the translation

information to the access control logic. If the TLB contains a translated entry for the virtual address, the

access control logic determines whether access is permitted. If access is permitted, the MMU outputs

the appropriate physical address corresponding to the virtual address. If access is not permitted, the

MMU signals the CPU to abort.

If the TLB misses (that is, it does not contain a translated entry for the virtual address), the translation

table walk hardware is invoked to retrieve the translation information from a translation table in physical

memory. Once retrieved, the translation information is placed into the TLB, possibly overwriting an existing

value. The entry to be overwritten is chosen by cycling sequentially through the TLB locations.

When the MMU is turned off (for example, on reset), the virtual address is output directly onto the physical

address bus.

6.1 MMU Program-Accessible Registers

The ARM processor provides several 32-bit registers that determine the operation of the MMU. The format

for these registers and a brief description is shown in Figure 6-1 on page 39. Each register is discussed

in more detail within the section that describes its use.

Data is written to and read from the MMU registers using the ARM CPU MRC and MCR coprocessor

instructions.

38

ARM PROCESSOR MMU

ADVANCE DATA BOOK v2.0

June 1997

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