AD9260AS(2000) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD9260AS
(Rev.:2000)

High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate

Analog Devices 

AD9260

1KPOT

U5

8

2.5/3V

1

NC

7

NC

AD780R +VIN 2

6

VOUT

TEMP 3

5 TRIM

GNDS 4

C18

0.1␮F

C19

0.1␮F

VCC2

R10

1k⍀

AGND

R3 R12

15k⍀ 15k⍀

JP10

C14

0.1␮F

1V

R4 R13

10k⍀ 10k⍀

R11

49.9⍀

C17

10␮F

+

C15

0.1␮F

AD817R

U6

VCC2

AGND

R9

1k⍀

Q1

2N2222

R8

390⍀

AGND

Figure 70. Evaluation Board External Reference Circuitry

C12 +

0.1␮F

VREFEXT

C13

10␮F

Table IX. Evaluation Board Recommended Resistance Value

for External Bias Resistor

Resistor

Value

2 kΩ

4 kΩ

8 kΩ

16 kΩ

Clock Speed

(max)

20 MHz

10 MHz

5 MHz

2.5 MHz

Power

Consumption

585 mW

325 mW

200 mW

150 mW

• Data Interfacing Controls: The data interfacing controls

(RESETB, CSB, READ, DAV) are all accessible via SMA

connectors (J2–J5) as illustrated in Figure 71 within the data

interfacing control block. The RESETB, CSB and READ

connections are each supplied with two sets or resistor pin

cups to allow the user to pull-up or pull-down each signal to

a fixed state. R5, R6 and R30 will terminate to ground, while

R7, R28 and R29 terminate to DRVDD. The DAV and

OTR signals are also directly connected to the data output

connector P1. All interfacing controls are buffered through

the CMOS line driver 74HC541.

• Buffered Output Data: The twos complement output data

is buffered through two CMOS noninverting bus transceivers

(U2 and U3) and made available at pin connector P1 as

illustrated in Figure 71 within the data output block.

• Jumper Controlled Reference Source: The choice of

reference for the AD9260 can easily be varied between 1.0 V,

2.5 V or external, by using Jumpers JP5, JP6, JP7 and JP9 as

illustrated in Figure 71 within the reference configuration

block. To obtain the desired reference see Table X.

Table X. Evaluation Board Reference Pin Configuration

Reference

Voltage

Connect Jumper

Input Voltage

(pk-pk FS)

2.5 V

1.0 V

External

JP7

JP6

JP5, JP9 and JP10

4.0 V

1.6 V

4.0 V

The external reference circuitry, is illustrated in Figure 70. By

connecting or disconnecting JP10, the external reference can be

configured for either 1.0 V or 2.5 V. That is, by connecting JP10,

the external reference will be configured to provide a 2.5 V

reference. By leaving JP10 open, the external reference will be

configured to provide a 1.0 V reference.

• Flexible DC or AC Coupled External Clock Inputs: As

illustrated in Figure 71, the AD9260 Evaluation Board is

designed to allow the user the flexibility of selecting how to

connect the external clock source. It is also equipped with a

playpen area for experimenting with optional clock drivers or

crystals.

• Selecting DC or AC Coupled External Clock:

DC Coupled: To directly drive the clock externally via the

CLKIN connector, connect JP11 and disconnect JP12. Note:

50 Ω terminated by R27.

AC Coupled: To ac couple the external clock and level shift it

to midsupply, connect JP12 and disconnect JP11. Note: 50 Ω

terminated by R27.

• Flexible Input Signal Configuration Circuitry: The

AD9260 Evaluation Board’s Input Signal Configuration Block

is illustrated in Figure 72. It is comprised of an input signal

summing amplifier (U7), a variable input signal common-

mode generator (U10) and a pair of amplifiers (U8 and U9)

that configure the input into a differential signal and drive it,

through a pair of isolation resistors, into the input pins of

AD9260. The user can either input a signal or dual signal

into the evaluation board via the two SMA connectors (J6 and

J7) labeled IN-1 or IN-2.

The user should refer to the Driving the Input section of the data

sheet for a detailed explanation of how the inputs are to be driven

and what amplifier requirements are recommended.

• Selecting Single or Dual Signal Input: The input ampli-

fier (U7) can either be configured as a dual input signal

inverting summer or a single tone inverting buffer. This

flexibility will allow for slightly better noise performance in

the single tone mode due to the inherent noise gain differ-

ence in the two amplifier configurations. An optional feed-

back capacitor (C9) was added to allow the user additional

out-of band filtering of the input signal if needed.

–30–

REV. B

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