DA28F320S5-110 View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DA28F320S5-110 Datasheet PDF : 50 Pages
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E
28F160S5, 28F320S5
6.2.5
#
AC CHARACTERISTICS - WRITE OPERATIONS
Table 21. Write Operations(1,6), TA = –40°C to +85°C
Versions(6)
5V ± 5%
Valid for All
5V ± 10% VCC
Speeds
Sym
Parameter
Notes Min Max
Unit
W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX# ) Going Low
2
1
µs
W2 tELWL
CEX# Setup to WE# Going Low
10
ns
(tWLEL)
(WE# Setup to CEX# Going Low)
0
ns
W3 tWLWH
WE# Pulse Width
40
ns
(tELEH)
(CEX# Pulse Width)
50
ns
W4 tDVWH (tDVEH) Data Setup to WE# (CEX# ) Going High
3
40
ns
W5 tAVWH (tAVEH) Address Setup to WE# (CEX# ) Going High
3
40
ns
W6 tWHEH
CEX# Hold from WE# High
10
ns
(tEHWH)
(WE# Hold from CEX# High)
0
ns
W7 tWHDX (tEHDX) Data Hold from WE# (CEX# ) High
5
ns
W8 tWHAX (tEHAX) Address Hold from WE# (CEX# ) High
5
ns
W9 tWHWL
WE# Pulse Width High
30
ns
(tEHEL)
(CEX# Pulse Width High)
25
ns
W10 tSHWH (tSHEH) WP# VIH Setup to WE# (CEX# ) Going High
100
ns
W11 tVPWH (tVPEH) VPP Setup to WE# (CEX# ) Going High
2
100
ns
W12 tWHGL (tEHGL) Write Recovery before Read
0
ns
W13 tWHRL (tEHRL) WE# High to STS in RY/BY# Low
90 ns
W14 tQVSL
WP# VIH Hold from Valid SRD
2,4
0
ns
W15 tQVVL
VPP Hold from Valid SRD, STS in RY/BY# High
2,4
0
ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.
4. VPP should be at VPPH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Figures 13 through 15 for testing characteristics.
ADVANCE INFORMATION
45
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