AD9705-DPG2-EBZ(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9705-DPG2-EBZ
(Rev.:RevD)
(Rev.:RevD)
Analog Devices
AD9705-DPG2-EBZ Datasheet PDF : 42 Pages
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AD9704/AD9705/AD9706/AD9707
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9707
PIN 1
INDICATOR
DB7 1
DB6 2
DVDD 3
DB5 4
DB4 5
DB3 6
DB2 7
DB1 8
AD9707
TOP VIEW
(Not to Scale)
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 OTCM
18 AVDD
17 PIN/SPI/RESET
Data Sheet
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER GROUND
PLANE FOR ENHANCED ELECTRICAL AND THERMAL
PERFORMANCE.
Figure 3. AD9707 Pin Configuration
Table 9. AD9707 Pin Function Descriptions
Pin No.
Mnemonic Description
28 to 32, 1, DB12 to DB1 Data Bit 12 to Data Bit 1.
2, 4 to 8
3
DVDD
Digital Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
9
DB0 (LSB)
Least Significant Data Bit (LSB).
10, 26
DCOM
Digital Common.
11
CLKVDD
Clock Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
12
CLK+
Positive Differential Clock Input.
13
CLK−
Negative Differential Clock Input.
14
CLKCOM
Clock Common.
15
CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial
data clock input.
16
MODE/SDIO In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos
complement. In SPI mode, this pin acts as SPI data input/output.
17
PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
18
AVDD
Analog Supply Voltage (1.7 V to 3.6 V). DVDD, AVDD, and CLKVDD must be at the same supply voltage.
19
OTCM
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
20
IOUTB
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
21
IOUTA
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
22
ACOM
Analog Common.
23
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V
reference output when internal reference is activated. Requires a 0.1 µF capacitor to ACOM when internal
reference is activated.
24
FS ADJ
Full-Scale Current Output Adjust.
25
SLEEP/CSB
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).
27
DB13 (MSB) Most Significant Data Bit (MSB).
EPAD
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced
electrical and thermal performance.
Rev. D | Page 12 of 42
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