AD9705-DPG2-EBZ(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9705-DPG2-EBZ
(Rev.:RevD)
(Rev.:RevD)
Analog Devices
AD9705-DPG2-EBZ Datasheet PDF : 42 Pages
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AD9704/AD9705/AD9706/AD9707
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
R/W N1 N0 A4 A3 A2 A1 A0 D7N D6N D5N
D30 D20 D10 D00
Figure 72. Serial Register Interface Timing, MSB First Write
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
R/W N1 N0 A4 A3 A2 A1 A0
D7
D6N D5N
D30 D20 D10 D00
Figure 73. Serial Register Interface Timing, MSB First Read
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
Figure 74. Serial Register Interface Timing, LSB First Write
Data Sheet
CSB
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W
D0
D10 D20
D4N D5N D6N D7N
Figure 75. Serial Register Interface Timing, LSB First Read
CSB
SCLK
SDIO
tDS
tSCLK
tPWH
tPWL
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 76. Timing Diagram for SPI Register Write
CSB
SCLK
SDIO I1
tSU
tHLD
I0
D7
D6
D5
Figure 77. Timing Diagram for SPI Register Read
SPI REGISTER MAP
Table 15.
Mnemonic
SPI CTL
Data
Version
CALMEM
MEMRDWR
MEMADDR
MEMDATA
Addr
0x00
0x02
0x0D
0x0E
0x0F
0x10
0x11
Bit 7
SDIODIR
DATAFMT
CALSTAT
Bit 6
DATADIR
CALEN
Bit 5
SWRST
CALMEM[1]
MEMADDR[5]
MEMDATA[5]
Bit 4
LNGINS
DCLKPOL
CALMEM[0]
MEMADDR[4]
MEMDATA[4]
Bit 3
PDN
DESKEW
VER[3]
SMEMWR
MEMADDR[3]
MEMDATA[3]
Bit 2
Sleep
CLKDIFF
VER[2]
DIVSEL[2]
SMEMRD
MEMADDR[2]
MEMDATA[2]
Bit 1
CLKOFF
VER[1]
DIVSEL[1]
MEMADDR[1]
MEMDATA[1]
Bit 0
EXREF
CALCLK
VER[0]
DIVSEL[0]
UNCAL
MEMADDR[0]
MEMDATA[0]
Rev. D | Page 32 of 42
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