AD9705-DPG2-EBZ(RevD) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9705-DPG2-EBZ
(Rev.:RevD)
(Rev.:RevD)
Analog Devices
AD9705-DPG2-EBZ Datasheet PDF : 42 Pages
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Data Sheet
AD9704/AD9705/AD9706/AD9707
SPI REGISTER DESCRIPTIONS
Table 16. SPI CTL—Register 0x00
Mnemonic Bit No. Direction (I/O)
SDIODIR 7
I
DATADIR 6
I
SWRST
5
I
LNGINS
4
I
PDN
3
I
Sleep
2
I
CLKOFF
1
I
EXREF
0
I
Default
1
0
0
0
0
0
0
0
Description
0 = SDIO pin configured for input only during data transfer (4-wire interface).
1 = SDIO pin configured for input or output during data transfer (3-wire interface).
0 = Serial data uses MSB first format.
1 = Serial data uses LSB first format.
1 = initiates a software reset; this bit is set to 0 upon reset completion.
0 = uses 1 byte preamble (5 address bits).
1 = uses 2 byte preamble (13 address bits).
1 = shuts down DAC output current internal band gap reference.
1 = DAC output current off.
1 = disables internal master clock.
0 = internal band gap reference.
1 = external reference.
Table 17. Data—Register 0x02
Mnemonic Bit No.
Direction (I/O)
DATAFMT 7
I
DCLKPOL 4
I
DESKEW
3
I
CLKDIFF
2
I
CALCLK
0
I
Default
0
0
0
0
0
Description
0 = unsigned binary input data format
1 = twos complement input data format
0 = data latched on DATACLK rising edge always
1 = data latched on DATACLK falling edge (only active in DESKEW mode)
0 = DESKEW mode disabled.
1 = DESKEW mode enabled (adds a register in digital data path to remove
skew in received data; one clock cycle of latency is introduced)
0 = single-ended clock input
1 = differential clock input
0 = calibration clock disabled
1 = calibration clock enabled
Table 18. Version—Register 0x0D
Mnemonic Bit No.
Direction (I/O)
VER[3:0]
[3:0]
O
Default
0000
Description
Hardware version identifier
Table 19. CALMEM—Register 0x0E
Mnemonic Bit No.
Direction (I/O)
CALMEM[1:0] [5:4]
O
DIVSEL[2:0] [2:0]
I
Default
00
000
Description
Calibration memory
00 = uncalibrated
01 = self-calibration
10 = not used
11 = user input
Calibration clock divide ratio from DAC clock rate
000 = divide by 256
001 = divide by 128
…
110 = divide by 4
111 = divide by 2
Rev. D | Page 33 of 42
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