MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

19. RESET

The MC80F0704/0708/0804/0808 supports various kinds of reset

as below.

• Power-On Reset (POR)

• RESET (external reset circuitry)

RESET

POR

(Power-On Reset)

Noise Canceller

Address Fail reset

PFD

(Power-Fail Detection)

WDT

(WDT Timeout Reset)

• Watchdog Timer Timeout Reset

• Power-Fail Detection (PFD) Reset

• Address Fail Reset

S

Q

Overflow

R

Clear

BIT

Internal

RESET

Figure 19-1 RESET Block Diagram

The on-chip POR circuit holds down the device in RESET until

VDD has reached a high enough level for proper operation. It will

eliminate external components such as reset IC or external resis-

tor and capacitor for external reset circuit. In addition that the RE-

SET pin can be used to normal input port R35 by setting “POR”

and “R35EN” bit Configuration Area(20FFH) in the Flash pro-

gramming. When the device starts normal operation, its operating

parameters (voltage, frequency, temperature...etc) must be met.

.Table 19-1 shows on-chip hardware initialization by reset action.

On-chip Hardware

Program counter

(PC)

RAM page register (RPR)

G-flag

(G)

Operation mode

Initial Value

(FFFFH) - (FFFEH)

0

0

Main-frequency clock

On-chip Hardware

Peripheral clock

Watchdog timer

Control registers

Power fail detector

Initial Value

Off

Disable

Refer to Table 8-1 on page 30

Disable

Table 19-1 Initializing Internal Status by Reset Action

The reset input is the RESET pin, which is the input to a Schmitt

Trigger. A reset in accomplished by holding the RESET pin low

for at least 8 oscillator periods, within the operating voltage range

and oscillation stable, it is applied, and the internal state is initial-

ized. After reset, 65.5ms (at 4 MHz) add with 7 oscillator periods

are required to start execution as shown in Figure 19-3 .

Internal RAM is not affected by reset. When VDD is turned on,

the RAM content is indeterminate. Therefore, this RAM should

be initialized before read or tested it.

VCC

7036P

10kΩ

+

10uF

to the RESET pin

When the RESET pin input goes to high, the reset operation is re-

leased and the program execution starts at the vector address

stored at addresses FFFEH - FFFFH.

Figure 19-2 Simple Power-on-Reset Circuit

A connection for simple power-on-reset is shown in Figure 19-2 .

October 31, 2011 Ver 1.03

95

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