MC80F0704/0708/0804/0808
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the basic
clock pulses which provide the system clock to be supplied to the
CPU and the peripheral hardware. It contains main-frequency
clock oscillator. The system clock operation can be easily ob-
tained by attaching a crystal or a ceramic resonator between the
XIN and XOUT pin, respectively. The system clock can also be ob-
tained from the external oscillator. In this case, it is necessary to
input a external clock signal to the XIN pin and open the XOUT
pin. There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry is
STOP
INOSC
Main OSC
Stop
INOSC
XIN
XOUT
OSC
ONP
fXIN
Circuit Circuit
Int OSC
Circuit
INCLK
MUX
through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must be observed.
To the peripheral block, the clock among the not-divided original
clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided.
Peripheral clock is enabled or disabled by STOP instruction. The
peripheral clock is controlled by clock control register
(CKCTLR). See "11. BASIC INTERVAL TIMER" on page 45
for details.
SLEEP
fEX
Clock Pulse
Generator
(÷2)
Internal
system clock
INOSC
PRESCALER
INOSC (IN4MCLK/IN2MCLK/
IN4MCLKXO/IN2MCLKXO)
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
7~3 2~0
÷1 ÷2 ÷4 ÷8 ÷16
Configuration Option Register (20FFH)
fEX (Hz)
PS0
PS1
PS2
PS3
PS4
PS5
Frequency 4M
2M
1M
4M
period
250n 500n
1u
500K
2u
250K
4u
125K
8u
÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
PS6
PS7
PS8
PS9
PS10
62.5K 31.25K 15.63K 7.183K 3.906K
16u
32u
64u 128u 256u
PS11 PS12
1.953K 976
512u 1.024m
Figure 10-1 Block Diagram of Clock Generator
10.1 Oscillation Circuit
XIN and XOUT are the input and output, respectively, a inverting
amplifier which can be set for use as an on-chip oscillator, as
shown in Figure 10-2 .
Xout
Recommendation
C1
Crystal/Ceramic Oscillator C1,C2 = 10~30pF
C2
Xin
Cautions 1. The recommended load capacitor values(C1,C2,C3,C4) are common value
Vss
but may not be appropriate for some crystal or ceramic resonator.
Figure 10-2 Oscillator Connections
Note: When using a system clock oscillator, carry out wiring in
the broken line area in Figure 10-2 to prevent any effects from wir-
October 31, 2011 Ver 1.03
43