MC80F0804D View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

MC80F0804D

8-BIT SINGLE-CHIP MICROCONTROLLERS

Unspecified 

MC80F0704/0708/0804/0808

11. BASIC INTERVAL TIMER

The MC80F0704/0708/0804/0808 has one 8-bit Basic Interval

Timer that is free-run and can not stop. Block diagram is shown

in Figure 11-1 . In addition, the Basic Interval Timer generates

the time base for watchdog timer counting. It also provides a Ba-

sic interval timer interrupt (BITIF).

The 8-bit Basic interval timer register (BITR) is increased every

internal count pulse which is divided by prescaler. Since prescal-

er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024

of the oscillator frequency. As the count overflow from FFH to

00H, this overflow causes the interrupt to be generated.

The Basic Interval Timer is controlled by the clock control regis-

ter (CKCTLR) shown in Figure 11-2. If the RCWDT bit is set to

“1”, the clock source of the BITR is changed to the internal RC

oscillation.

When write "1" to bit BTCL of CKCTLR, BITR register is

cleared to "0" and restart to count-up. The bit BTCL becomes "0"

after one machine cycle by hardware.

If the STOP instruction executed after writing "1" to bit RCWDT

of CKCTLR, it goes into the internal RC oscillated watchdog tim-

er mode. In this mode, all of the block is halted except the internal

RC oscillator, Basic Interval Timer and Watchdog Timer. More

detail informations are explained in Power Saving Function. The

bit WDTON decides Watchdog Timer or the normal 7-bit timer.

Source clock can be selected by lower 3 bits of CKCTLR.

BITR and CKCTLR are located at same address, and address

0F2H is read as a BITR, and written to CKCTLR.

Note: All control bits of Basic interval timer are in CKCTLR reg-

ister which is located at same address of BITR (address ECH). Ad-

dress ECH is read as BITR, written to CKCTLR. Therefore, the

CKCTLR can not be accessed by bit manipulation instruction.

XIN PIN

Internal RC OSC

RCWDT

÷8

÷16

÷32

÷64

÷128

÷256

÷512

÷1024

MUX

8-bit up-counter

1 source

clock

overflow

BITR

0

[0F2H]

clear

Select Input clock 3

BCK[2:0]

[0F2H]

Basic Interval Timer

clock control register

RCWDT

CKCTLR

BTCL

Read

Internal bus line

BITIF

Basic Interval

Timer Interrupt

To Watchdog timer (WDTCK)

Figure 11-1 Block Diagram of Basic Interval Timer

October 31, 2011 Ver 1.03

45

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