MC80F0704/0708/0804/0808
Source clock
BIT overflow
Binary-counter 1
WDTR
WDTIF interrupt
WDT reset
2
3
0
1
2
Counter
Clear
n
3
WDTR ← “1000_0011B”
3
0
Counter
Clear
Match
Detect
reset
Figure 12-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is generated,
which drives the RESET pin low to reset the internal hardware.
set is generated in sub clock mode.
The main clock oscillator also turns on when a watchdog timer re-
October 31, 2011 Ver 1.03
49