PIC16LF876AT-I/ML View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LF876AT-I/ML Datasheet PDF : 218 Pages
| |||
PIC16F87X
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Max Units
Conditions
100
Thigh Clock high time
100 kHz mode
4.0
—
µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
µs Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
—
101
Tlow Clock low time
100 kHz mode
4.7
—
µs Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
µs Device must operate at a
minimum of 10 MHz
SSP Module
0.5TCY
—
102
Tr
SDA and SCL rise 100 kHz mode
—
1000 ns
time
400 kHz mode
20 + 0.1Cb 300
ns Cb is specified to be from
10 to 400 pF
103
Tf
SDA and SCL fall time 100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1Cb 300
ns Cb is specified to be from
10 to 400 pF
90
Tsu:sta START condition
100 kHz mode
setup time
400 kHz mode
4.7
—
µs Only relevant for Repeated
0.6
—
µs START condition
91
Thd:sta START condition hold 100 kHz mode
time
400 kHz mode
4.0
—
µs After this period, the first clock
0.6
—
µs pulse is generated
106
Thd:dat Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
107
Tsu:dat Data input setup time 100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
Tsu:sto STOP condition setup 100 kHz mode
time
400 kHz mode
4.7
—
µs
0.6
—
µs
109
Taa Output valid from
100 kHz mode
clock
400 kHz mode
—
3500 ns (Note 1)
—
—
ns
110
Tbuf Bus free time
100 kHz mode
400 kHz mode
4.7
—
µs Time the bus must be free
1.3
—
µs before a new transmission
can start
Cb Bus capacitive loading
—
400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement that
Tsu:dat ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is
released.
DS30292C-page 172
2001 Microchip Technology Inc.
Share Link: 