PIC18F2423/2523/4423/4523
TABLE 1-2: PIC18F2423/2523 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin Buffer
PDIP,
SOIC
QFN
Type
Type
Description
MCLR/VPP/RE3
MCLR
VPP
RE3
1 26
Master Clear (input) or programming voltage (input).
I ST
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
P
Programming voltage input.
I ST
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
9
6
Oscillator crystal or external clock input.
I ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
I CMOS External clock source input. Always associated with pin
function, OSC1. (See related OSC1/CLKI, OSC2/CLKO
pins.)
I/O TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 7
Oscillator crystal or clock output.
O—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O—
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the instruction cycle rate.
I/O TTL General purpose I/O pin.
Legend:
TTL =
ST =
O=
I2C =
TTL compatible input
Schmitt Trigger input with CMOS levels
Output
I2C™/SMBus
CMOS = CMOS compatible input or output
I
= Input
P
= Power
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39755C-page 14
© 2009 Microchip Technology Inc.