FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

If the host terminates a read or write operation

in the FDC, the ID information in the result

phase is dependent upon the state of the MT bit

and EOT byte. Refer to Table 20.

to "01" indicating abnormal termination, sets

the ND bit in Status Register 1 to "1" indicating a

sector not found, and terminates the Read Data

Command.

At the completion of the Read Data command,

the head is not unloaded until after the Head

Unload Time Interval (specified in the Specify

command) has elapsed. If the host issues

another command before the head unloads,

then the head settling time may be saved

between subsequent reads.

If the FDC detects a pulse on the nINDEX pin

twice without finding the specified sector

(meaning that the diskette's index hole passes

through index detect logic in the drive twice), the

FDC sets the IC code in Status Register 0

After reading the ID and Data Fields in each

sector, the FDC checks the CRC bytes. If a

CRC error occurs in the ID or data field, the

FDC sets the IC code in Status Register 0 to

"01" indicating abnormal termination, sets the

DE bit flag in Status Register 1 to "1", sets the

DD bit in Status Register 2 to "1" if CRC is

incorrect in the ID field, and terminates the Read

Data Command. Table 21 describes the effect

of the SK bit on the Read Data command

execution and results. Except where noted in

Table 21, the C or R value of the sector address

is automatically incremented (see Table 23).

Table 20 - Effects of MT and N Bits

MAXIMUM TRANSFER

MT N

CAPACITY

FINAL SECTOR READ

FROM DISK

0 1 256 x 26 = 6,656

1 1 256 x 52 = 13,312

0 2 512 x 15 = 7,680

1 2 512 x 30 = 15,360

26 at side 0 or 1

26 at side 1

15 at side 0 or 1

15 at side 1

0 3 1024 x 8 = 8,192

1 3 1024 x 16 = 16,384

8 at side 0 or 1

16 at side 1

52

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