FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

Sense Drive Status

Sense Drive Status obtains drive status

information. It has not execution phase and

goes directly to the result phase from the

command phase. Status Register 3 contains

the drive status information.

Specify

The Specify command sets the initial values for

each of the three internal times. The HUT

(Head Unload Time) defines the time from the

end of the execution phase of one of the

read/write commands to the head unload state.

The SRT (Step Rate Time) defines the time

interval between adjacent step pulses. Note that

the spacing between the first and second step

pulses may be shorter than the remaining step

pulses. The HLT (Head Load Time) defines the

time between when the Head Load signal goes

high and the read/write operation starts. The

values change with the data rate speed selection

and are documented in Table 27. The values

are the same for MFM and FM.

Table 27 - Drive Control Delays (ms)

HUT

SRT

2M 1M 500K 300K 250K 2M 1M 500K 300K 250K

0 64 128 256 426 512 4

8

16 26.7 32

14

8

16 26.7 32 3.75 7.5 15 25 30

.. ..

..

..

..

..

..

..

..

..

..

E 56 112 224 373 448 0.5

1

2 3.33 4

F 60 120 240 400 480 0.25 0.5

1 1.67 2

2M

00

64

01

0.5

02

1

..

..

7F

63

7F

63.5

HLT

1M

500K

300K

250K

128

256

426

512

1

2

3.3

4

2

4

6.7

8

..

..

..

.

126

252

420

504

127

254

423

508

The choice of DMA or non-DMA operations is made by the ND bit. When this bit is "1", the non-DMA

mode is selected, and when ND is "0", the DMA mode is selected. In DMA mode, data transfers are

signaled by the FDRQ pin. Non-DMA mode uses the RQM bit and the FINT pin to signal data

transfers.

61

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