FDC37B80X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B80X

PC98/99 compliant enhanced super I/O controller with Keyboard / Mouse Wake-Up / 5 Volt Operation

SMSC -> Microchip 

FIFO

MODE

ONLY

BIT 3

0

0

0

1

0

0

INTERRUPT

IDENTIFICATION

REGISTER

Table 30 - Interrupt Control Table

INTERRUPT SET AND RESET FUNCTIONS

PRIORITY INTERRUPT INTERRUPT

BIT 2 BIT 1 BIT 0 LEVEL

TYPE

SOURCE

0

0

1

-

None

None

INTERRUPT

RESET CONTROL

-

1

1

0 Highest Receiver Line Overrun Error, Reading the Line

Status

Parity Error,

Status Register

Framing Error or

Break Interrupt

1

0

0 Second Received

Receiver Data Read Receiver

Data

Available

Buffer or the FIFO

Available

drops below the

trigger level.

1

0

0 Second

Character

No Characters Reading the

Timeout

Have Been

Receiver Buffer

Indication

Removed From Register

or Input to the

RCVR FIFO

during the last 4

Char times and

there is at least 1

char in it during

this time

0

1

0 Third

Transmitter

Holding

Register

Empty

Transmitter

Holding Register

Empty

Reading the IIR

Register (if Source

of Interrupt) or

Writing the

Transmitter

Holding Register

0

0

0 Fourth

MODEM

Status

Clear to Send or

Data Set Ready

or Ring Indicator

or Data Carrier

Detect

Reading the

MODEM Status

Register

69

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