FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

mid-sector, and the FDC will continue to

complete the sector as if a hardware TC was

received. The only difference between these

implicit functions and TC is that they return

"abnormal termination" result status. Such

status indications can be ignored if they were

expected.

Note that when the host is sending data to the

FIFO of the FDC, the internal sector count will

be complete when the FDC reads the last byte

from its side of the FIFO. There may be a delay

in the removal of the transfer request signal of

up to the time taken for the FDC to read the last

16 bytes from the FIFO. The host must tolerate

this delay.

Result Phase

The generation of FINT determines the

beginning of the result phase. For each of the

commands, a defined set of result bytes has to

be read from the FDC before the result phase is

complete. These bytes of data must be read out

for another command to start.

RQM and DIO must both equal "1" before the

result bytes may be read. After all the result

bytes have been read, the RQM and DIO bits

switch to "1" and "0" respectively, and the CB bit

is cleared, indicating that the FDC is ready to

accept the next command.

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