FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

EPP

SIGNAL

nWRITE

PD<0:7>

INTR

EPP NAME

nWrite

Address/Data

Interrupt

WAIT

nWait

DATASTB nData Strobe

RESET

nReset

ADDRSTB

PE

SLCT

nERR

PDIR

nAddress

Strobe

Paper End

Printer

Selected

Status

Error

Parallel Port

Direction

TABLE 40 - EPP PIN DESCRIPTIONS

TYPE

O

I/O

I

I

O

O

O

I

I

EPP DESCRIPTION

This signal is active low. It denotes a write operation.

Bi-directional EPP byte wide address and data bus.

This signal is active high and positive edge triggered. (Pass

through with no inversion, Same as SPP).

This signal is active low. It is driven inactive as a positive

acknowledgement from the device that the transfer of data is

completed. It is driven active as an indication that the

device is ready for the next transfer.

This signal is active low. It is used to denote data read or

write operation.

This signal is active low. When driven active, the EPP

device is reset to its initial operational mode.

This signal is active low. It is used to denote address read

or write operation.

Same as SPP mode.

Same as SPP mode.

I Same as SPP mode.

O This output shows the direction of the data transfer on the

parallel port bus. A low means an output/write condition and

a high means an input/read condition. This signal is

normally a low (output/write) unless PCD of the control

register is set or if an EPP read cycle is in progress.

Note 1: SPP and EPP can use 1 common register.

Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP

cycle. For correct EPP read cycles, PCD is required to be a low.

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