FDC37B78X View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

Manufacturer

FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

Register Definitions

The register definitions are based on the

standard IBM addresses for LPT. All of the

standard printer ports are supported. The

additional registers attach to an upper bit

decode of the standard LPT port definition to

avoid conflict with standard ISA devices. The

port is equivalent to a generic parallel port

interface and may be operated in that mode.

The port registers vary depending on the mode

field in the ecr. The table below lists these

dependencies. Operation of the devices in

modes other that those specified is undefined.

NAME

data

ecpAFifo

dsr

dcr

cFifo

ecpDFifo

tFifo

cnfgA

cnfgB

ecr

TABLE 42 - ECP REGISTER DEFINITIONS

ADDRESS (Note 1)

ECP MODES

FUNCTION

+000h R/W

000-001

Data Register

+000h R/W

011

ECP FIFO (Address)

+001h R/W

All

Status Register

+002h R/W

All

Control Register

+400h R/W

010

Parallel Port Data FIFO

+400h R/W

011

ECP FIFO (DATA)

+400h R/W

110

Test FIFO

+400h R

111

Configuration Register A

+401h R/W

111

Configuration Register B

+402h R/W

All

Extended Control Register

Note 1: These addresses are added to the parallel port base address as selected by configuration

register or jumpers.

Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.

MODE

TABLE 43 - MODE DESCRIPTIONS

DESCRIPTION*

000 SPP mode

001 PS/2 Parallel Port mode

010 Parallel Port Data FIFO mode

011 ECP Parallel Port mode

100 EPP mode (If this option is enabled in the configuration registers)

101 Reserved

110 Test mode

111 Configuration mode

*Refer to ECR Register Description

99

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