AD1816A
Figure 14 illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams man-
aged by the AD1816A. Any ADC or DAC data stream can be intercepted by the port, shipped to an external DSP or ASIC manipu-
lated, and returned to any DAC summing path or to the ADC.
PGA
AUDIO/
MODEM
Σ∆ ADC
MA
AUDIO
Σ∆ DAC
Σ
MA
MA
MA
SERIAL PORT INTERFACE
FORMAT FIFO
MUSIC
SYNTHESIZER
FORMAT FIFO
PLUG AND PLAY
ISA BUS
PARALLEL
INTERFACE
I2S SERIAL PORT (0)
I2S SERIAL PORT (1)
Figure 14. DSP Serial Port
ISA INTERFACE
AD1816A Chip Registers
Table II, Chip Register Diagram, details the AD1816A direct register set available from the ISA Bus. Prior to any accesses by the
host, the PC I/O addressable ports must be configured using the Plug and Play Resources.
Table II. Chip Register Diagram
Register Type-Register Name
Register PC I/O Address
Plug and Play
ADDRESS
WRITE_DATA
READ_DATA
0x279
0xA79
Relocatable in Range 0x203 – 0x3FF
Sound System Codec
CODEC REGISTERS
0x(SS Base+0 – SS Base+15)
Relocatable in Range 0x100 – 0x3FF
See Table V
SoundBlaster Pro
Music0: Address (w), Status (r)
Music0: Data (w)
Music1: Address (w)
Music1: Data (w)
Mixer Address (w)
Mixer Data (w)
Reset (w)
Music0: Address (w)
Music0: Data (w)
Input Data (r)
Status (r), Output Data (w)
Status (r)
(SB Base) Relocatable in Range 0x100 – 0x3F0
(SB Base+1)
(SB Base+2)
(SB Base+3)
(SB Base+4)
(SB Base+5)
(SB Base+6 or 7)
(SB Base+8)
(SB Base+9)
(SB Base+A or +B)
(SB Base+C or +D)
(SB Base+E or +F)
REV. A
–21–