AD1816AJS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD1816AJS Datasheet PDF : 52 Pages
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AD1816A
ADDRESS
00 (0x00)
01 (0x01)
02 (0x02)
03 (0x03)
04 (0x04)
05 (0x05)
06 (0x06)
07 (0x07)
08 (0x08)
09 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
32 (0x20)
33 (0x21)
34 (0x22)
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29 )
42 (0x2A)
43 (0x2B)
44 (0x2C)
45 (0x2D)
46 (0x2E)
7
PIE
LVM
LFMM
LS1M
LS0M
LMVM
LCDM
LSYM
LVDM
LLM
MCM
LAGC
WSE
DS1
3DDM
CPD
Table VIII. Sound System Indirect Registers
(High Byte)
6
5
4
3
2
1
RES
CIE
TIE
VIE
DIE
RIE
JIE
VPSR [15.8]
VCSR [15:8]
RES
LVA [5:0]
RES
LFMA [5:0]
RES
LS1A [5:0]
RES
LS0A [5:0]
PBC [15:8]
PCC [15:8]
CBC [15:8]
CCC [15:8]
TBC [15:8]
TCC [15:8]
RES
LMVA [4:0]
RES
LCDA [4:0]
RES
LSYA [4:0]
RES
LVDA [4:0]
RES
LLA [4:0]
M20
RES
MCA [4:0]
LAS [2:0]
LAG [3:0]
CDE
RES
CNP
RES
DS0
DIT
RES
ADR
I1T
FSMR [15:8]
S1SR [15:8]
S0SR [15:8]
RES
PCR [15:8]
RES
3DD [3:0]
RES
RES
MB0R [15:8]
MB1R [15:8]
RES
PIW
PIR
PAA
PDA PDP
VER [15:8]
RES
(Low Byte)
0
7
6
5
4
3
2
1
0
LBTD [7:0]
SIE
TE
XC1
XC0
VPSR [7:0]
VCSR [7:0]
RVM
RES
RVA [5:0]
RFMM RES
RFMA [5:0]
RS1M RES
RS1A [5:0]
RS0M RES
RS0A [5:0]
PBC [7:0]
PCC [7:0]
CBC [7:0]
CCC [7:0]
TBC [7:0]
TCC [7:0]
RMVM
RES
RMVA [4:0]
RCDM
RES
RCDA [4:0]
RSYM
RES
RSYA [4:0]
RVDM
RES
RVDA [4:0]
RLM
RES
RLA [4:0]
PIM
RES
PIA [3:0]
RES
RAGC
RAS [2:0]
RAG [3:0]
COF [3:0]
I2SF1 [1:0]
I2SF0 [1:0]
I0T
CPI
PBI
FMI
I1I
I01
DFS [2:0]
FMSR [7:0]
S1SR [7:0]
S0SR [7:0]
RES
PCR [7:0]
RES
POM
RES
POA [4:0]
RES
VMU VUP VDN
BM [4:0]
MB0R [7:0]
MB1R [7:0]
PTB
3D PD3D GPSP RES
DM
RES
VER [7:0]
RES
[00] INDIRECT LOW BYTE TMP
7
6
5
4
3
2
1
0
7
6
5
RES
LBTD [7:0] Low Byte Temporary Data holding latch for register pair writes;
Written on any write to [SSBase + 2],
Read from [SSBase + 2] when the indirect address is 0x00.
[01] INTERRUPT ENABLE AND EXTERNAL CONTROL
7
6
5
4
3
2
1
0
7
PIE CIE TIE VIE DIE RIE JIE SIE TE
65
DEFAULT = [0xXX]
4
3
2
1
0
LBTD [7:0]
4
3
RES
DEFAULT = [0x0102]
2
1
0
XC1 XC0
XC0
RW
External Control 0. The state of this bit is reflected on the XCTL0 pin. This pin is also muxed with
PCLKO. COF must be greater than 0x1011 for PCLKO to be disabled, see SS [32].
XC1
RW
External Control 1. The state of this bit is reflected on the XCTL1 pin. XCTL1 may also be used for
Ring-In Interrupt. Open drain output, contains internal pull-up ~ 0.5 mA.
TE
RW
Timer Enable Bit.
SIE
RW
SoundBlaster Interrupt Enable; This bit must be set to enable Current Count Timer.
0
SoundBlaster Interrupt disabled
1
SoundBlaster Interrupt enabled
JIE
RW
Joystick Interrupt Enable;
0
Joystick Interrupt disabled
1
Joystick Interrupt enabled
REV. A
–31–
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