CS61535A-IL1 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS61535A-IL1

T1/E1 Line Interface

Cirrus Logic 

CS61535A

ter the falling edge of TCLK. The CS61534 re-

quires 50 ns of hold time on TPOS and TNEG

after the falling edge of TCL, and 0 ns of setup

time.

6) LOS occurs after 31 consecutive zeros on the

CS61534. For the CS61535A LOS occurs after

175 zeros.

7) Since the CS61535A receivers are continu-

ously calibrated, there is no need to issue a reset

to initialize the receiver timing as with the

CS61534.

Using the CS61535A for SONET

The CS61535A can be applied to SONET VT1.5

and VT2.0 interface circuits as shown in Fig-

ure A5. The SONET data rate is 51.84 MHz, and

has 6480 bits per frame (125 us per frame). An

individual T1 frame (193 bits per frame) or PCM-

30 frame (256 bits per frame) has its data mapped

into the 6480 bit SONET frame. The mapping

does not result in a uniform spacing between

sucessive T1 (or E1) bits. Rather, for locked VT

applications, gaps as large as 24 T1 bit periods or

32 E1 bit periods can exist between successive

bits. With floating VTs, the gaps can be even

larger.

The circuit in Figure A5 eliminates the demulti-

plexing jitter in a two-step approach. The first

step uses a FIFO which is filled at a 51.84 MHz

rate (when T1 or E1 bits are present), and which

is emptied at a sub-multiple of the 51.84 rate. The

FIFO is emptied only when it contains data.

When the FIFO is empty the output clock is not

pulsed.

The sub-multiple rate chosen should be slightly

faster than the target rate (1.544 or 2.048 MHz),

but as close to the target rate as possible. For

51.84 MHz

Div By

6480 to

193 bit

(or 256 bit)

Mapping

Circuit

TCLK1

TSER

RSER

RCLK1

Empty

Write

FIFO Clock

TSER

FIFO

RSER

RCLK2

CS62180B

TCLK2

TPOS

TNEG

RPOS

RNEG

RCLK2

Jitter

Attenuator

Driver

CS61535A

Receiver

Figure A5. SONET Application

32

DS40F2

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